The present invention generally relates to semiconductor devices and more particularly to a semiconductor device formed on a so-called epitaxial substrate in which a semiconductor layer is grown on a semiconductor substrate epitaxially.
With the advancement in the art of ultra-fine lithography, semiconductor devices are miniaturized more and more. Today, so-called submicron or sub-halfmicron devices are studied intensively.
In such recent submicron or sub-halfmicron devices, there tends to arise a problem in that low density crystal defects, which cannot be avoided even in a high-quality single crystal Si substrate, cause an adversary effect on the operation of the semiconductor device formed on the Si substrate. Thus, in order to screen the effect of the crystal defects in the Si substrate, it is proposed to use an epitaxial substrate in which a Si layer is formed on the Si substrate epitaxially, for the substrate of highly miniaturized semiconductor devices.
When a conventional Si substrate is used for carrying a CMOS device, it is well known that there tends to occur a problem of latch-up of a parasitic thyristor that is formed in the Si substrate as a result of formation of diffusion regions of the CMOS device. When the semiconductor device is miniaturized, the parasitic thyristor easily causes a latch up and the normal operation of the semiconductor device is seriously disturbed. The use of the foregoing epitaxial substrate is quite effective for eliminating the problem of the latch-up of the parasitic thyristor. Further, the leakage current of the semiconductor devices is reduced significantly when such an epitaxial substrate is used for the substrate of the semiconductor devices.
FIG. 1 shows the principle of elimination of the problem of latch-up of a CMOS integrated circuit by the use of an epitaxial substrate.
Referring to FIG. 1, there is formed a p.sup.- -type epitaxial layer 1A of Si on a Si layer 1 of the p.sup.+ -type, and the p-type epitaxial layer 1A is formed with diffusion regions 3 and 5 as a source region or a drain region of an n-channel MOS transistor T.sub.1. Further, the p-type epitaxial layer 1A is formed with an n-type well 2 adjacent to the n-channel MOS transistor T.sub.1, and diffusion regions 4 and 6 are formed therein as a source region or a drain region of a p-channel MOS transistor T.sub.2 that is formed in the n-type well 2.
It should be noted that the CMOS integrated circuit of FIG. 1 includes a gate insulation film 7 and a gate electrode 9 on the epitaxial layer 1A in correspondence to the channel region of the MOS transistor T.sub.1. Further, the CMOS integrated circuit includes a gate insulation film 8 and a gate electrode 10 on the epitaxial layer 1A in correspondence to the n-type well 2. Further, the epitaxial layer 1A and the n-type well 2 include a p.sup.+ -type diffusion region 11 and an n.sup.+ -type diffusion region 12 respectively, for stabilizing the potential thereof.
In the CMOS integrated circuit of FIG. 1, it can be seen that there is formed a parasitic thyristor in the Si substrate such that the thyristor includes a parasitic npn transistor 13 and a parasitic pnp transistor 14, wherein the parasitic npn transistor 13 includes a base formed of the epitaxial layer 1A itself, an emitter formed of the n.sup.+ -type diffusion region 3 and a collector formed of the n-type well 2. On the other hand, the parasitic pnp transistor 14 includes a base formed of the n-type well 2 itself, an emitter of the p.sup.+ -type diffusion region 4 and a collector of the p-type epitaxial layer 1A.
In the construction of FIG. 1, it can be seen that the base-emitter resistance R.sub.1 of the transistor 13 is reduced substantially by disposing the low-resistance p.sup.+ -type substrate 1 underneath the epitaxial layer 1A. Thus, the turning-on of the transistor 13, and hence the turning-on of the parasitic thyristor, is substantially impeded. It should be noted that the p.sup.+ -type Si substrate 1 forms a low-resistance current path between the base and the emitter of the transistor 13.
Meanwhile, a semiconductor integrated circuit generally includes a protection circuit in a part of the semiconductor substrate forming the semiconductor integrated circuit for avoiding electrostatic damaging of semiconductor devices in the integrated circuit by a voltage surge. Generally, such a protection circuit is formed in the vicinity of an input or electrode pad.
In the case of a semiconductor integrated circuit formed on an epitaxial substrate noted above, it should be noted that the turning-on of the protective circuit tends to be impeded similarly to the case of the parasitic thyristor because of the presence of the low resistance Si substrate underneath the Si epitaxial layer when a voltage surge comes in. Thus, there is a tendency that a semiconductor integrated circuit formed on an epitaxial substrate tends to accumulate electric charges therein. The electric charges thus accumulated are ultimately discharged, causing an electrostatic damaging to the semiconductor devices in the integrated circuit.
FIG. 2 shows an example of a conventional protection circuit used conventionally in semiconductor integrated circuit in a state in which the protection circuit is provided in the epitaxial substrate of FIG. 1, wherein those parts of FIG. 2 corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.
Referring to FIG. 2, the epitaxial substrate 1A of the p.sup.- -type is formed with a p-type well 21, wherein the p-type well 21 includes a diffusion region 21A of the n.sup.+ -type and another diffusion region 21B of the n.sup.+ -type such that a field oxide film 22 is interposed between the diffusion region 21A and the diffusion region 21B. The diffusion region 21A is connected to an electrode pad 20 for external connection via a conductor line 20a. The diffusion region 21B is grounded. Further, in order to maintain the potential of the p-type well 21 at the ground level, the well 21 is grounded via a p-type diffusion region 21C formed in the well 21.
In the protection circuit of FIG. 2, it should be noted that an external signal arrived at the electrode pad 20 reaches the diffusion region 21A via the conductor line 20a and forwarded further to an internal circuit not illustrated, via another conductor line 20b. The internal circuit may include the CMOS circuit shown in FIG. 1.
In the protection circuit of FIG. 2, it should be noted that there is formed a lateral bipolar transistor 21a in the p-type well 21 such that the lateral bipolar transistor 21a includes an emitter formed of the n.sup.+ -type diffusion region 21B and a collector formed of the n.sup.+ -type diffusion region 21A. The lateral bipolar transistor 21a thus formed conducts when a large positive surge is applied to the electrode pad 20 and dissipates the electric charges of the surge to the ground. When a large negative surge is applied to the electrode pad 20, on the other hand, a forward biasing occurs in the p-n junction formed between the n.sup.+ -type diffusion region 21A and the p-type well 21, and the electric charges associated with the surge is dissipated to the ground from the diffusion region 21A through the well 21C and further through the diffusion region 21C.
In the case the protection circuit of FIG. 2 is formed in an epitaxial substrate as in the case of FIG. 1, however, it has been discovered that the resistance of the semiconductor devices in the semiconductor integrated circuit against ESD (electrostatic discharge) experiences a serious deterioration. It is believed that this deterioration of the resistance against ESD is caused as a result of the diffusion of the p-type dopant from the highly doped Si substrate 1 to the epitaxial layer 1A. Such a diffusion of the p-type dopant tends to occur in the fabrication of the semiconductor integrated circuit as a result of thermal annealing processes used therein.
When such a diffusion of the p-type dopant occurs, the concentration level of the p-type dopant in the epitaxial layer 1A is increased and the resistance of the epitaxial layer 1A is decreased accordingly. In other words, there appears a state in which the base and emitter of the lateral bipolar transistor 21a forming the protection circuit are effectively connected. In such a state, the turning-on of the transistor 21a is substantially impeded even when a large positive surge voltage is applied to the terminal pad 20, and the surge voltage is applied to the protection circuit as well as to the internal circuit of the integrated circuit, causing an electrostatic damaging therein. Further, the electric charges associated with the voltage surge are accumulated in the protection circuit itself and damages the lateral bipolar transistor 21a.
In the event a large negative voltage surge is applied to the external terminal pad 20, on the other hand, a very large current is caused to flow due to the low resistance of the p-type well 21, wherein such a large current destroys the protection circuit as a result of Joule heating.
FIG. 4 shows the diffusion of B from the Si substrate 1 to the epitaxial layer 1A for the case in which the epitaxial substrate is subjected to a thermal annealing process conducted at 1000.degree. C. for 30 minutes. In the experiment of FIG. 4, it should be noted that the epitaxial layer 1A is formed with a thickness of about 2 .mu.m and the Si substrate contains B with a concentration level of about 1.times.10.sup.19 cm.sup.-3. The epitaxial layer 1A, in turn, is substantially free from doping in the as-formed state and contains B with a concentration level of about 1.times.10.sup.15 cm.sup.-3
Referring to FIG. 4, it can be seen that the sharp transition of the B concentration level, observed at the interface between the Si substrate 1 and the epitaxial layer 1A before the thermal annealing process, becomes diffused substantially after the thermal annealing process, indicating that a substantial amount of B atoms have diffused into the epitaxial layer 1A. In the illustrated example, it can be seen that a boundary defining the region in which the B concentration level is 1.times.10.sup.19 cm.sup.-3 has moved into the epitaxial layer 1A with a distance of about 1 .mu.m.
FIG. 5 shows the result of measurement of the resistance of the p-type well 21 in the epitaxial layer 1A for various thicknesses of the epitaxial layer 1A.
Referring to FIG. 5, the result designated as "BULK" is for the case in which the measurement was conducted on a simple Si substrate by regarding the bulk of the p-type Si substrate as the p-type well 21. In this case, in which the thickness of the epitaxial layer 1A can be regarded substantially infinite, it was observed that the resistance of the well 21 is high and takes a value of about 3500 .OMEGA.. On the other hand, this value of the resistance decreases with decreasing thickness of the epitaxial layer 1A and reaches less than 100 .OMEGA. when the thickness of the layer 1A becomes smaller than about 2 .mu.m. This indicates that there is a substantial diffusion of B from the p.sup.+ -type Si substrate 1 as explained with reference to FIG. 4.
FIG. 6 shows the relationship between the voltage in which the protection circuit is damaged by ESD and the thickness of the epitaxial layer 1A, wherein the test of the ESD is conducted by accumulating a positive or negative voltage surge in a capacitor of 200 pF capacitance and applying the voltage thus accumulated to the protection circuit repeatedly for 5 times with an interval of 0.5 seconds. The damaging of the protection circuit thus tested is evaluated by measuring a leakage current.
Referring to FIG. 6, it can be seen that the voltage or failure voltage in which the foregoing electrostatic damaging occurs in the protection circuit decreases with decreasing thickness of the epitaxial layer 1A for any of the positive and negative surges and reaches a voltage of as low as about 200V when the thickness of the epitaxial layer 1A is reduced to about 2 .mu.m. Thus, it can be seen that the diffusion of B from the p.sup.+ -type Si substrate 1 to the epitaxial layer 1A explained with reference to FIG. 4 causes a profound effect on the operation of the semiconductor integrated circuit that is formed on the epitaxial layer 1A.